The present invention is in the field of programmable logic devices (PLD's) and, more particularly, is related to the use of look-up tables (LUTs) in logic elements (LEs) of PLD's where not only are multiple stages of arithmetic performed in each LUT but, also, the LUTs are configurable to accomplish multiple non-arithmetic functions with reduced input sharing requirements.
A common use for LE logic in a PLD is to perform arithmetic operations. LEs of conventional PLDs provide arithmetic functionality with 4-input LUTs. (We refer to a LUT with “x” inputs as an “x-LUT.”) FIG. 1 is a block diagram of a conventional 4-LUT 100.
The 4-LUT 100 can be thought of, functionally, as two 3-LUTs 102 and 104. The 4-LUT 100 performs arithmetic, with the ability to add two bits in each 3-LUT 102 and 104. A multiplexer 106 selects between the outputs of the 3-LUTs 102 and 104, using the fourth data input D to the 4-LUT 100 as a select line to control the output of the multiplexer 106. Conventional implementations of LUT arithmetic use one 3-LUT of a 4-LUT to generate the sum from two summand signals and the carry_in of the previous stage. The other 3-LUT generates the carry_out of the stage from the same three input signals (i.e. the two summand signals and the carry_in of the previous stage). A benefit of such a scheme is that an arithmetic sum output is generated by the same output circuitry that may be used to generate separate arithmetic functions. This allows arithmetic to be performed without requiring any additional multiplexers for selection between different outputs. FIG. 2 is a block diagram of a LUT 200, illustrating the LUT 100 configured according to the conventional approach.